Integrated circuit package with air gap

ABSTRACT

An integrated circuit (IC) package comprises an IC wafer. A first portion is arranged adjacent to the IC wafer. A second portion is arranged adjacent to the IC wafer and that is spaced from the first portion. The first and second portions comprise at least one of annealed glass paste (AGP) and epoxy. A layer is arranged adjacent to the first and second portions and creates an air gap between the layer, the first and second portions and the IC wafer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of U.S. patent application Ser. No.11/328,979 filed Jan. 10, 2006, which claims the benefit of U.S.Provisional Application Nos. 60/756,828, filed Jan. 6, 2006, 60/714,454,filed on Sep. 6, 2005, and 60/730,568, filed on Oct. 27, 2005, and is acontinuation-in-part of U.S. patent application Ser. No. 10/892,709,filed on Jul. 16, 2004, which is a continuation in part of U.S. patentapplication Ser. No. 10/272,247, filed on Oct. 15, 2002, the contents ofwhich are hereby incorporated by reference in their entirety.

TECHNICAL FIELD

This invention relates to integrated circuits, and more particularly tointegrated circuits with annealed glass paste arranged on a siliconwafer.

BACKGROUND

Precision frequency references are required in many types of electronicdevices such as cellular phones and other handheld devices. Crystaloscillators are typically used to provide the precision frequencyreference in these electronic devices. However, crystal oscillators haveseveral inherent disadvantages including large bulky size, fragility,and high cost. In addition, the size and cost of crystal oscillators isrelated to the resonant frequency so that as the frequency increases,the size decreases, and the cost and fragility may rapidly increase. Asthe size of electronic devices continues to decrease, the use of crystaloscillators becomes more problematic due to the size, fragility, andcost limitations.

Semiconductor oscillators have been a poor alternative to crystaloscillators and are generally unsuitable for use as a precisionfrequency reference due to excessive variation in the oscillatingfrequency, especially with changes in temperature.

SUMMARY OF THE INVENTION

An integrated circuit (IC) package comprises a IC wafer and an annealedglass paste (AGP) layer that is arranged adjacent to the IC wafer.

In other features, a molding material encapsulates at least part of theIC wafer and the AGP layer. The AGP layer is arranged on at least oneside of the IC wafer. The AGP layer is arranged on a plurality ofdisjoint areas on at least one side of the IC wafer. A layer of aconductive material that is arranged on a portion of the AGP layer.

In other features, the IC wafer comprises a circuit component arrangedin the IC wafer. The AGP layer is arranged between the circuit componentand the molding material. The circuit component comprises at least oneof an oscillator and an inductor. The inductor comprises a spiralinductor. The molding material encapsulates a portion of the IC wafer.The AGP layer comprises a glass frit. The AGP layer is arranged adjacentto the IC wafer using one of a screen printing, dipping and masking.

In other features, the conductive material comprises one of a conductiveepoxy and a conductive epoxy paint. The layer of the conductive materialis arranged on the AGP layer by dipping the IC package in a containercontaining the conductive material.

An integrated circuit comprises a temperature sensor that senses atemperature of the integrated circuit. A memory module stores datarelating to oscillator calibrations and selects one of the oscillatorcalibrations as a function of the sensed temperature. An oscillatormodule generates a reference signal having a frequency. A phase lockedloop module includes a feedback loop having a feedback loop parameterand selectively adjusts the feedback loop parameter based on theselected one of the oscillator calibrations.

In other features, the phase locked loop module comprises a fractionalphase locked loop and the feedback loop parameter is a ratio of ascaling factor. The fractional phase locked loop comprises a phasefrequency detector module that communicates with the oscillator moduleand that receives the reference frequency. A charge pump modulecommunicates with the phase frequency detector module. A voltagecontrolled oscillator module communicates with the charge pump moduleand generates an output frequency. A scaling module communicates withthe voltage controlled oscillator module and the phase frequencydetector module, selectively adjusts the output frequency based on firstand second scaling factors, and adjusts a ratio of the first and secondscaling factors based on the selected one of the oscillatorcalibrations.

In other features, the first and second scaling factors are divisorsequal to N and N+1, and wherein N is an integer greater than zero. Thephase locked loop module comprises a Sigma Delta fractional phase lockedloop module and the feedback loop parameter includes modulation of ascaling divisor. The Sigma Delta fractional phase locked loop modulecomprises a phase frequency detector module that communicates with theoscillator module and that receives the reference frequency. A chargepump module communicates with the phase frequency detector module. Avoltage controlled oscillator module communicates with the charge pumpmodule and that generates an output frequency. A scaling modulecommunicates with the voltage controlled oscillator module and the phasefrequency detector module and selectively divides the output frequencyby first and second scaling factors. A Sigma Delta modulator adjustsmodulation of the scaling module between the first and second scalingfactors based on the selected one of the oscillator calibrations. Thefirst and second scaling factors are divisors equal to N and N+1, whereN is an integer greater than zero.

An integrated circuit comprises temperature sensing means for sensing atemperature of the integrated circuit. Memory means for storing datarelating to oscillator calibrations and for selecting one of theoscillator calibrations as a function of the sensed temperature.Oscillating means generates a reference signal having a frequency basedon the oscillator calibrations. Phase locked loop means, that includes afeedback loop having a feedback loop parameter, selectively adjusts thefeedback loop parameter based on the selected one of the oscillatorcalibrations.

In other features, the phase locked loop means comprises a fractionalphase locked loop and the feedback loop parameter is a ratio of ascaling factor. The fractional phase locked loop comprises phasefrequency detector means, that communicates with the oscillating means,for receiving the reference frequency. Charge pump means generatesvoltage and communicates with the phase frequency detector means.Voltage controlled oscillator means, that communicates with the chargepump means, generates an output frequency. Scaling means, thatcommunicates with the voltage controlled oscillator means and the phasefrequency detector means, selectively adjusts the output frequency basedon first and second scaling factors and adjusts a ratio of the first andsecond scaling factors based on the selected one of the oscillatorcalibrations.

In other features, the first and second scaling factors are divisorsequal to N and N+1, and wherein N is an integer greater than zero. Thephase locked loop means comprises a Sigma Delta fractional phase lockedloop and the feedback loop parameter includes modulation of a scalingdivisor. The Sigma Delta fractional phase locked loop comprises phasefrequency detector means, that communicates with the oscillator means,for receiving the reference frequency. Charge pump means generates avoltage and communicates with the phase frequency detector means.Voltage controlled oscillator means, that communicates with the chargepump means, generates an output frequency. Scaling means, thatcommunicates with the voltage controlled oscillator means and the phasefrequency detector means, selectively divides the output frequency byfirst and second scaling factors. Sigma Delta modulating means adjustsmodulation of the scaling means between the first and second scalingfactors based on the selected one of the oscillator calibrations. Thefirst and second scaling factors are divisors equal to N and N+1, whereN is an integer greater than zero.

A method for operating an integrated circuit comprises sensing atemperature of the integrated circuit; storing data relating tooscillator calibrations; selecting one of the oscillator calibrations asa function of the sensed temperature; generating a reference signalhaving a frequency based on the oscillator calibrations; and selectivelyadjusting a feedback loop parameter of a phase locked loop based on theselected one of the oscillator calibrations.

In other features, the phase locked loop comprises a fractional phaselocked loop and the feedback loop parameter is a ratio of a scalingfactor. The phase locked loop comprises a Sigma Delta fractional phaselocked loop and the feedback loop parameter includes modulation of ascaling divisor.

An integrated circuit package comprises an integrated circuit thatcomprises a temperature sensor that senses a temperature of theintegrated circuit. A memory module stores data relating to oscillatorcalibrations and that selects one of the oscillator calibrations as afunction of the sensed temperature. An oscillator module generates areference signal having a frequency that is based on the selected one ofthe oscillator calibrations. A packaging material encases at least partof the integrated circuit and has a low dielectric loss.

In other features, the packaging material includes at least one materialselected from a group consisting of polychlorotrifluoroethylene,fluorinated ethylene propylene copolymer, perfluoroalkoxy, and acopolymer of ethylene and tetrafluoroethylene. The packaging materialincludes a low dielectric loss plastic.

An integrated circuit package comprises an integrated circuit thatcomprises an oscillator module that generates a reference signal havinga frequency that is based on one of a plurality of oscillatorcalibration settings. A packaging material encases at least part of theintegrated circuit and has a low dielectric loss.

In other features, the integrated circuit further comprises atemperature sensor that senses a temperature of the integrated circuit.A memory module stores the oscillator calibration settings. Thepackaging material includes at least one material selected from a groupconsisting of polychlorotrifluoroethylene, fluorinated ethylenepropylene copolymer, perfluoroalkoxy, and a copolymer of ethylene andtetrafluoroethylene. The packaging material includes a low dielectricloss plastic.

A method for providing an integrated circuit package comprises providingan integrated circuit; encasing the integrated circuit in a packagingmaterial that has a low dielectric loss; sensing a temperature of theintegrated circuit during operation; storing data relating to oscillatorcalibrations; selecting one of the oscillator calibrations as a functionof the sensed temperature; and generating a reference signal having afrequency that is based on the selected one of the oscillatorcalibrations.

In other features, the packaging material includes at least one materialselected from a group consisting of polychlorotrifluoroethylene,fluorinated ethylene propylene copolymer, perfluoroalkoxy, and acopolymer of ethylene and tetrafluoroethylene. The packaging materialincludes a low dielectric loss plastic.

A method for providing an integrated circuit package comprises providingan integrated circuit; selecting one of a plurality of oscillatorcalibration settings; generating a reference signal having a frequencythat is based on the one of the plurality of oscillator calibrationsettings; and encasing the integrated circuit in a packaging materialthat has a low dielectric loss.

In other features, the method comprises sensing a temperature of theintegrated circuit; and selecting the one of the plurality of oscillatorcalibration settings based on the sensed temperature. The packagingmaterial includes at least one material selected from a group consistingof polychlorotrifluoroethylene, fluorinated ethylene propylenecopolymer, perfluoroalkoxy, and a copolymer of ethylene andtetrafluoroethylene. The packaging material includes a low dielectricloss plastic.

An integrated circuit package comprises an integrated circuit thatcomprises temperature sensing means for sensing a temperature of theintegrated circuit. Storing means stores data relating to oscillatorcalibrations and for selecting one of the oscillator calibrations as afunction of the sensed temperature. Oscillating means generates areference signal having a frequency that is based on the selected one ofthe oscillator calibrations. Packaging means encases at least part ofthe integrated circuit and having a low dielectric loss.

In other features, the packaging means includes at least one materialselected from a group consisting of polychlorotrifluoroethylene,fluorinated ethylene propylene copolymer, perfluoroalkoxy, and acopolymer of ethylene and tetrafluoroethylene. The packaging meansincludes a low dielectric loss plastic.

An integrated circuit package comprises an integrated circuit thatcomprises oscillating means for generating a reference signal having afrequency that is based on one of a plurality of oscillator calibrationssettings and packaging means for encasing at least part of theintegrated circuit and having a low dielectric loss.

In other features, the integrated circuit further comprises temperaturesensing means for sensing a temperature of the integrated circuit.Storing means stores oscillator calibration data. The packaging meansincludes at least one material selected from a group consisting ofpolychlorotrifluoroethylene, fluorinated ethylene propylene copolymer,perfluoroalkoxy, and a copolymer of ethylene and tetrafluoroethylene.The packaging means includes a low dielectric loss plastic.

An integrated circuit package comprises an integrated circuit thatcomprises a temperature sensor that senses a temperature of theintegrated circuit and a memory module that stores oscillatorcalibrations and that selects one of the oscillator calibrations as afunction of the sensed temperature. An oscillator module generates areference signal having a frequency that is based on the selected one ofthe oscillator calibrations. An epoxy layer adheres a glass layer to theintegrated circuit. A packaging material encases at least part of theglass layer and the integrated circuit.

In other features, the glass layer is located between adjacent toportions of the integrated circuit that include the oscillator module.The oscillator module includes an on-chip inductor and wherein the glasslayer is located adjacent to portions of the integrated circuit thatinclude on-chip inductor. The glass layer includes a cavity that definesan air gap and wherein the cavity is adjacent to potions of theintegrated circuit that include the oscillator module. The glass layerincludes a cavity that defines an air gap and wherein the cavity isadjacent to potions of the integrated circuit that include an inductorof the oscillator module.

An integrated circuit package comprises an integrated circuit thatcomprises temperature sensing means for sensing a temperature of theintegrated circuit and storing means for storing oscillator calibrationsand for selecting one of the oscillator calibrations as a function ofthe sensed temperature. Oscillating means generates a reference signalhaving a frequency that is based on the selected one of the oscillatingmeans calibrations. Means attaches a glass layer to the integratedcircuit. Packaging means encases at least part of the glass layer andthe integrated circuit.

In other features, the glass layer is located adjacent to portions ofthe integrated circuit that include the oscillating means. Theoscillating means includes an on-chip inductor and wherein the glasslayer is located adjacent to portions of the integrated circuit thatinclude on-chip inductor. The glass layer includes a cavity that definesan air gap and wherein the cavity is adjacent to potions of theintegrated circuit that include the oscillating means. The glass layerincludes a cavity that defines an air gap and wherein the cavity isadjacent to potions of the integrated circuit that include an inductorof the oscillating means.

A method for providing an integrated circuit package comprises sensing atemperature of an integrated circuit; storing oscillator calibrations;selecting one of the oscillator calibrations as a function of the sensedtemperature; generating a reference signal having a frequency that isbased on the selected one of the oscillator calibrations; and attachinga glass layer to the integrated circuit; and encasing at least part ofthe glass layer and the integrated circuit in a packaging material.

In other features, the method includes locating the glass layer adjacentto portions of the integrated circuit that include the oscillatormodule. The oscillator module includes an on-chip inductor and furthercomprising locating the glass layer adjacent to portions of theintegrated circuit that include on-chip inductor. The glass layerincludes a cavity that defines an air gap and further comprisinglocating the cavity adjacent to potions of the integrated circuit thatinclude the oscillator. The glass layer includes a cavity that definesan air gap and further comprising locating the cavity adjacent topotions of the integrated circuit that include an inductor of theoscillator.

An integrated circuit (IC) package comprises an IC wafer. A firstportion is arranged adjacent to the IC wafer. A second portion isarranged adjacent to the IC wafer and is spaced from the first portion.The first and second portions comprise at least one of annealed glasspaste (AGP) and epoxy. A layer is arranged adjacent to the first andsecond portions and creates an air gap between the layer, the first andsecond portions and the IC wafer.

In other features, the IC wafer comprises a silicon wafer. A moldingmaterial encapsulates at least part of the IC wafer, the layer and thefirst and second portions. The layer comprises at least one of glass andsilicon. A conductive material is arranged adjacent to the first andsecond portions. The silicon wafer comprises a circuit component. Theair gap is arranged between the circuit component, the layer and thefirst and second portions. The circuit component comprises at least oneof an oscillator and an inductor. The inductor comprises a spiralinductor.

In other features, the first and second portions comprise glass frit.The first and second portions are applied to the silicon wafer using oneof a screen printing, dipping and masking. The conductive materialcomprises one of a conductive epoxy and conductive epoxy paint. Theconductive material is applied to the first and second portions bydipping the at least part of the IC package in a container containingthe conductive material. The layer has a first width that is less than asecond width of the silicon wafer. The IC wafer comprises bond pads. Thelayer has a first width that is less than a second width of the siliconwafer and further comprising bond pads that are located in an outerregion of the silicon wafer.

A method of providing an integrated circuit (IC) package, comprisesproviding an IC wafer; arranging a first portion adjacent to the ICwafer; arranging a second portion adjacent to the IC wafer and spacedfrom the first portion, wherein the first and second portions compriseat least one of annealed glass paste (AGP) and epoxy; and arranging alayer adjacent to the first and second portions, wherein the layercreates an air gap between the layer, the first and second portions andthe IC wafer.

In other features, the IC wafer comprises a silicon wafer. The methodfurther includes encapsulating at least part of the IC wafer, the layerand the first and second portions. The layer comprises at least one ofglass and silicon. The method further includes arranging a conductivematerial adjacent to the first and second portions. The method furtherincludes arranging the air gap between the circuit component, the layerand the first and second portions. The circuit component comprises atleast one of an oscillator and an inductor. The method further includesthe inductor comprises a spiral inductor. The first and second portionscomprise glass frit. The method further includes applying the first andsecond portions to the silicon wafer using one of a screen printing,dipping and masking. The conductive material comprises one of aconductive epoxy and conductive epoxy paint. The layer has a first widththat is less than a second width of the silicon wafer. The methodfurther includes providing bond pads on the IC wafer in an outer regionof the silicon wafer.

An integrated circuit (IC) package comprises an IC wafer comprising acircuit and a “C”-shaped layer that is arranged adjacent to thesubstrate and that creates an air gap between the “C”-shaped layer andthe circuit of the IC wafer.

In other features, a molding material that encapsulates at least part ofthe IC wafer and the “C”-shaped layer. The “C”-shaped layer comprises atleast one of glass and silicon. The circuit component comprises at leastone of an oscillator and an inductor. The inductor comprises a spiralinductor.

A method for providing an integrated circuit (IC) package comprisesproviding an IC wafer comprising a circuit and arranging a “C”-shapedlayer adjacent to the substrate, wherein the “C”-shaped layer creates anair gap between the “C”-shaped layer and the circuit of the IC wafer.

In other features, the method includes encapsulating at least part ofthe IC wafer and the “C”-shaped layer. The “C”-shaped layer comprises atleast one of glass and silicon. The circuit component comprises at leastone of an oscillator and an inductor. The inductor comprises a spiralinductor.

Further areas of applicability of the present invention will becomeapparent from the detailed description provided hereinafter. It shouldbe understood that the detailed description and specific examples, whileindicating the preferred embodiment of the invention, are intended forpurposes of illustration only and are not intended to limit the scope ofthe invention.

DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram showing an aspect of a crystal oscillatoremulator.

FIG. 2 is a table showing a relationship between temperature andcorrection factor.

FIG. 3 is a graph showing a relationship between temperature andcorrection factor.

FIG. 4 is a block diagram showing an aspect of a crystal oscillatoremulator.

FIG. 5 is a two-dimensional view of an aspect of a crystal oscillatoremulator connected to external impedances.

FIG. 6 is a detailed block diagram of an aspect of a crystal oscillatoremulator connected to an external impedance.

FIGS. 7A and 7B are diagrams showing relationships between an externalimpedance value and a digital value.

FIG. 8 is a block diagram of an aspect of an oscillator assembly forgenerating an output having a periodic waveform.

FIG. 9 is a block diagram of an aspect of a spread spectrum generator.

FIG. 10 is a flow diagram of an operation for emulating a crystaloscillator.

FIG. 11 is a block diagram of an aspect of a low power oscillator.

FIG. 12 is a block diagram of another aspect of a low power oscillator.

FIG. 13 is a functional block diagram of an integrated circuit includingone or more circuits and a crystal oscillator emulator that generates aclock signal for the one or more circuits.

FIG. 14 is a functional block diagram of an integrated circuit includinga processor and a crystal oscillator emulator that generates a clocksignal for the processor.

FIG. 15 is a functional block diagram of an integrated circuit includinga processor and a crystal oscillator emulator that generates a clocksignal for the processor and that employs an external component forsetting clock speed.

FIG. 16 is a functional block of an integrated circuit including one ormore circuits, a crystal oscillator emulator and a clock divider thatgenerates clock signals at one or more other clock frequencies.

FIG. 17 is a functional block of an integrated circuit including aprocessor, one or more circuits, a crystal oscillator emulator and aclock divider that generates clock signals at other clock frequencies.

FIG. 18 is a functional block of an integrated circuit including aprocessor, a graphic processor, one or more circuits, memory and acrystal oscillator emulator that generates clock signals.

FIG. 19 is a functional block diagram of an integrated circuit includinga processor and the low power oscillator of FIG. 11.

FIG. 20 is a functional block diagram illustrating an integrated circuitthat is encapsulated in a packaging material according to the prior art;

FIG. 21 is a functional block diagram illustrating an integrated circuitwith a temperature compensated on-chip semiconductor oscillator that isencapsulated in a packaging material having a low dielectric lossaccording to the present invention;

FIG. 22 illustrates one exemplary implementation of the integratedcircuit package of FIG. 21 in further detail;

FIG. 23 is a side cross-sectional view of an alternate integratedcircuit package including an on-chip semiconductor oscillator accordingto the present invention;

FIG. 24 is a side cross-sectional view of an alternate integratedcircuit package including an on-chip semiconductor oscillator accordingto the present invention;

FIG. 25 is a plan cross-sectional view illustrating the integratedcircuit package of FIG. 24 in further detail;

FIG. 26 is a functional block diagram illustrating tuning of a capacitorof an on-chip semiconductor oscillator based upon temperaturecompensation;

FIG. 27 is a functional block diagram of a fractional phase locked loop(PLL) that includes a temperature compensation input;

FIG. 28 is a functional block diagram of a Delta-Sigma fractional phaselocked loop that includes a temperature compensation input;

FIG. 29 is a flow chart illustrating steps for measuring samplingcalibration points and using a linear curve fitting algorithm togenerate calibration data between the sample calibration points;

FIG. 30 is a flow chart illustrating steps for measuring samplingcalibration points and using higher order curve fitting algorithms togenerate calibration data between the sample calibration points;

FIG. 31A is a functional block diagram of a hard disk drive;

FIG. 31B is a functional block diagram of a digital versatile disk(DVD);

FIG. 31C is a functional block diagram of a high definition television;

FIG. 31D is a functional block diagram of a vehicle control system;

FIG. 31E is a functional block diagram of a cellular phone;

FIG. 31F is a functional block diagram of a set top box;

FIG. 31G is a functional block diagram of a media player;

FIG. 32A is a side cross-sectional view of an alternate integratedcircuit package including an annealed glass paste and/or epoxy layerformed on at least part of a silicon wafer;

FIG. 32B is a side cross-sectional view of an alternate integratedcircuit package including an annealed glass paste and/or epoxy layerformed on at least part of a silicon wafer and a conductive materiallayer formed on at least part of the annealed glass paste and/or epoxylayer;

FIG. 32C is a side cross-sectional view of an alternate integratedcircuit package including spaced annealed glass paste layers formed onselected portions of a silicon wafer;

FIG. 32D is a side cross-sectional view of an alternate integratedcircuit package including spaced annealed glass paste and/or epoxylayers and conductive material layers formed on selected portions of asilicon wafer;

FIG. 33A is a side cross-sectional view of an alternate integratedcircuit package including an annealed glass paste and/or epoxy layer anda conductive material layer adjacent to circuits of a silicon wafer;

FIG. 33B is a side cross-sectional view of an alternate integratedcircuit package including an annealed glass paste and/or epoxy layer anda conductive material layer adjacent to an oscillator of a siliconwafer;

FIG. 33C is a side cross-sectional view of an alternate integratedcircuit package including an annealed glass paste and/or epoxy layer anda conductive material layer adjacent to an inductor of a silicon wafer;

FIG. 33D is a side cross-sectional view of an alternate integratedcircuit package including an annealed glass paste and/or epoxy layer anda conductive material layer adjacent to an inductor in an oscillatorcircuit of a silicon wafer;

FIGS. 34A-34D are side cross-sectional views of alternate integratedcircuit packages including annealed glass paste and/or epoxy portionsand a glass or silicon layer that create an air gap;

FIGS. 35A-35B are side cross-sectional views of alternate integratedcircuit packages including a “C”-shaped glass or silicon layer thatcreates an air gap;

FIGS. 36A-36C are side cross-sectional views of a wafer includingmultiple integrated circuit packages including annealed glass pasteand/or epoxy portions and a glass or silicon layer that create air gaps;

FIGS. 37A-37B are side-cross-sectional views of integrated circuitpackages including annealed glass paste and/or epoxy portions that havebeen coated with a conductive material; and

FIG. 38 illustrates exemplary steps of a method for fabricating theintegrated circuit packaging of FIGS. 32A-32D.

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

FIG. 1 shows an aspect of a crystal oscillator emulator 10 forgenerating an output signal 12 having a precise frequency. The crystaloscillator emulator 10 may be constructed on a single semiconductor dieusing any process including a Complementary-Metal-Oxide-Semiconductor(CMOS) process.

The crystal oscillator emulator 10 may include a semiconductoroscillator 14 to generate the output signal 12. Any type ofsemiconductor oscillator may be used including LC oscillators, RCoscillators, and ring oscillators. The semiconductor oscillator 12includes a control input 16 to vary the frequency of the output signal.The control input 16 may be any electrical input that effects acontrolled change in the output signal frequency such as the supplyvoltage of a ring oscillator and a voltage input to a varactor of an LCoscillator.

A non-volatile memory 18 includes calibration information 20 forcontrolling the output signal frequency as a function of temperature.Any type of non-volatile memory may be employed including contentaddressable memory (CAM). The calibration information 20 may include acorrection factor to be applied to the control input 16 of thesemiconductor oscillator 14 to control the output signal frequency. Thecalibration information 20 may be a function of a change in temperaturefrom a calibration temperature to an operating temperature, as well asbeing a function of absolute temperature.

A temperature sensor 22 may sense the temperature of the semiconductordie. Preferably, the temperature sensor is located on the semiconductordie in the vicinity of the semiconductor oscillator 14. Any type oftemperature sensor 22 may be used including thermistors and infrareddetectors. The temperature sensor 22 may be configured to measure achange in temperature from a baseline temperature or the presenttemperature.

FIG. 2 shows a storage technique 30 for storing the calibrationinformation 20 in the non-volatile memory 18. The storage technique 30may be any form of database including CAM, indexing schemes, look-uptables, and hash tables.

FIG. 3 shows a series of exemplary graphs 32 of correction factor valuesversus temperature for maintaining a constant output signal frequencyfor the crystal oscillator emulator 10. The data for constructing thecurve may be attained in any manner including device-level testing andbatch-mode testing.

Exemplary device-level testing may include testing each device todetermine correction factors to be applied to the semiconductoroscillator to maintain a constant output frequency with changes intemperature. In one scheme, a baseline value for the semiconductoroscillator control input is determined for a predetermined frequency andat a predetermined temperature of the semiconductor die of the devicesuch as the lowest operating temperature. The baseline value may bemeasured directly or interpolated from measurement of another devicecharacteristic. Baseline values may also be measured for each potentialoutput frequency. Also, baseline values for each potential outputfrequency may be extrapolated from the baseline value for thepredetermined frequency such as by using a known circuit relationship.The baseline values for each potential output frequency may be stored asabsolute values or as a ratio, a frequency factor, to compute thebaseline values from a single baseline value.

The temperature of the semiconductor die is then increased from aboutthe lowest operating temperature to about the maximum operatingtemperature in discrete steps. The number of discrete steps ispreferably limited to about six temperature levels to reduce testingcosts, but any number of discrete steps may be used. Preferably, anon-chip heater is used to heat the semiconductor die, but any means ofvarying the temperature of the semiconductor die may be employed. Ateach discrete step, the semiconductor die temperature and the correctionfactor for maintaining the output at a constant frequency may bemeasured.

The correction factor is preferably a ratio to be applied to thebaseline value to obtain an adjusted value for the control input. Thecalibration factor may range from any baseline value such as 1.Preferably, a single correction factor is computed for each temperaturestep, to be applied to the semiconductor oscillator to maintain theoutput signal at any one of a multitude of predetermined frequencies.For example, if a correction factor of 1.218 is determined to correspondto a change in temperature of 45 C, then the control input of thesemiconductor oscillator may be adjusted as a function of the correctionfactor such as by changing the control input in proportion to thecorrection factor. In another alternative, the correction factor may beapplied to the baseline value corresponding to the desired outputfrequency to generate a calibrated value to which the control input isadjusted. In another alternative, correction factors may be measuredcorresponding to each of several output frequencies at each temperaturestep.

Batch-mode testing of crystal oscillator emulators 10 to obtaincalibration information 20 may advantageously decrease costs by reducingthe number of measurements for a batch of semiconductor dies. Inbatch-mode testing, the testing results for a subset of crystaloscillator emulators 10 from the same batch of semiconductor dies may beused for all of the devices in the batch. The subset of crystaloscillator emulators that are tested may range from one to anyproportion of the total quantity of devices. For example, a singlecrystal oscillator emulator 10 may be tested and the resulting batchcalibration information stored in each of the devices in the batch. Inaddition, each of the crystal oscillator emulators 10 may be tested fora subset of calibration information such as the output frequency at abaseline temperature. The subset of device specific calibrationinformation may be used to modify the batch calibration informationstored in each device.

FIG. 4 shows another aspect of a crystal oscillator emulator 40. Thecrystal oscillator emulator 40 is similar to crystal oscillator 10 infunction with similar corresponding elements numbered in the range of40-52, except that crystal oscillator emulator 40 may also include oneor more of a heater 54, a controller 56, and a select input 58 alone orin combination.

The heater 54 may be located on the semiconductor die in the vicinity ofthe semiconductor oscillator 44 to provide a source of local heating.Any type of heater 54 may be used including transistor heaters andresistive heaters. The heater 54 may be operated in response to an inputfrom the temperature sensor 52 to control the temperature of thesemiconductor die. The heater 54 may increase the semiconductor dietemperature to a level that corresponds to one of the temperature levelsfor which correction factors have been determined. In addition, apackage having a high thermal impedance may enclose the crystaloscillator emulator 40.

In one case, the heater 54 may increase the semiconductor dietemperature to the maximum operating temperature. Here, during device orbatch level testing only the correction factor corresponding to themaximum operating temperature would have to be determined, leading toreduced costs.

The heater 54 may also be controlled to raise the semiconductor dietemperature to one of several predetermined temperature levels for whichcorrection factors have been determined. A second temperature sensor maysense an external temperature such as an ambient temperature or anassembly temperature. The heater 54 then may increase the semiconductordie temperature to the nearest of the predetermined temperature levelswhile continuously changing the control input during the temperaturetransition using extrapolated values computed from the correctionfactors.

The controller 56 may add extra functionality by for example controllingthe heater 54 in response to multiple temperature sensors ormanipulating the calibration information 50 to derive values for thecontrol input that correspond to intermediate temperatures. Thecontroller 56 may be any type of entity including a processor, logiccircuitry, and a software module.

The select input 58 may be used for selecting specific outputfrequencies from within a range of output frequencies. The outputfrequency may be selected as a function of the impedance of an externalcomponent connected to the select input. The external component may beused directly as a portion of the semiconductor oscillator to select theoutput frequency, or indirectly such as selecting values of impedancewithin a predetermined range may correspond to predetermined outputfrequencies. The external component may be any component, but ispreferably a passive component such as a resistor or capacitor.

FIG. 5 shows an aspect of a crystal oscillator emulator 100 having, forexample, two select pins 102 and 104 to connect to two externalimpedances 106 and 108. One or more pins may be used to interface to theexternal component(s). The crystal oscillator emulator 100 probes orderives information from the external components connected to the selectpins 102 and 104. The derived information may have three or morepredetermined level ranges that correspond to selected levels of theemulator characteristics. For example, a single pin connected to anexternal resistor may be used to select any one of 16 output frequencylevels. The resistance of the external resistor is preferably selectedto be one of 16 predetermined standard values. Each of the 16 values ofresistance corresponds to one of the 16 output frequency levels. Inaddition, low precision passive components are preferably used as theexternal components to reduce cost and inventory. Each externalcomponent may have multiple, N, predetermined nominal values that eachcorrespond to the selection of a predetermined characteristic level. Ifone pin is used, then N different characteristic levels may be selected.If two pins are used, then N*N different characteristic levels may beselected, and so forth for an increasing number of selection pins. Thetypes of device characteristics that for example may be selected includeoutput frequency, frequency tolerance, and baseline correction factor.For example, the crystal oscillator emulator 100 may have a singleselect pin 102 connected to an external resistor that may have a nominalvalue selected from a group of 16 predetermined values. Each of the 16predetermined values has a measured value range which corresponds to oneof 16 predetermined output frequency levels possibly ranging from 1 MHzto 100 MHz.

The external impedances 106 and 108 are preferably resistors,capacitors, or combinations of resistors and capacitors, but may be anycomponent that exhibits predominantly an inductance, resistance,capacitance, or combination thereof. The external impedances 106 and 108may be connected directly or indirectly from any energy source such asVdd and ground or any suitable reference to the pins 102 and 104. Forexample, the external impedance 106 may be connected through aresistor/transistor network to Vdd and through a capacitor network tothe select pin 102.

The crystal oscillator emulator 100 may determine a predetermined selectvalue corresponding to the measured value of the impedance connected toa select pin. Preferably, the impedance is selected to have a standardvalue such as nominal resistance values corresponding to resistorshaving a 10% tolerance (e.g. 470, 560, 680, . . . ) to reduce device andinventory costs. To account for measurement tolerances and the toleranceof the external impedance, a range of impedance values may correspond toa single select value. The select value is preferably a digital value,but may also be an analog value. For example, values of measuredresistance from 2400 ohms to 3000 ohms may be associated with a digitalvalue corresponding to 2. While values of measured resistance from 3001ohms to 4700 ohms are associated with a digital value corresponding to3. The measured resistance includes variations due to tolerances of theexternal impedance and the internal measurement circuit. The impedancemeasured at each select pin is used to determine a corresponding digitalvalue. The range of digital values may include 3 or more digital valuesand preferably range from 10 to 16 digital values per select pin. Thedigital values corresponding to each select pin may be used incombination to describe memory addresses. For example, a device havingthree select pins each to interface to impedance values that are mappedinto one of 10 digital values, may describe 1000 memory addresses orlookup table values. The contents of the storage locations correspondingto the memory addresses are used to set a value for an output orinternal characteristic of the device. Another exemplary device mayinclude two select pins, each configured to interface to externalimpedances that are mapped to a digital value within a range of 10values. The digital values in combination may describe 100 memoryaddresses or lookup table values that may each contain data for settinga characteristic of the crystal oscillator emulator 100.

FIG. 6 shows a block diagram of an aspect of a crystal oscillatoremulator 120. The crystal oscillator emulator 120 includes a select pin122 to interface to an external impedance 124 that is used for selectinga configuration of the crystal oscillator emulator 120. The externalimpedance 124 is similar in function and scope to the externalimpedances 116 and 118.

A measurement circuit 126 connected to the select pin 122 measures anelectrical characteristic that is a function of the external impedance124. For example, a current may be supplied to the external impedanceand the voltage that is developed across the external impedance 124 thenmeasured. Also, a voltage may be impressed across the external impedance124 and then measure the current. Any measurement technique formeasuring passive components may be used to measure the electricalcharacteristic including dynamic as well as static techniques. Exemplarymeasurement techniques include timing circuits, analog to digitalconverters (ADCs), and digital to analog converters (DACs). Preferably,the measurement circuit has a high dynamic range. The measurementcircuit 126 may generate an output having a value corresponding to thevalue of the external impedance 124. The output may be either digital oranalog. The same output value preferably represents a range of externalimpedance values to compensate for value variations such as tolerancesin the external impedance value, interconnect losses, and measurementcircuit tolerances due to factors including process, temperature, andpower. For example, all measured external impedance values ranging fromgreater than 22 up to 32 ohms may correlate to a digital output value of“0100”. While measured external impedance values ranging from greaterthan 32 up to 54 ohms may correlate to a digital output value of “0101”.The actual external impedance values are a subset of the measuredexternal impedance value to account for the value variations. Forexample, in the above cases the actual external impedance values mightbe from 24 to 30 ohms and from 36 to 50 ohms. In each case aninexpensive low precision resistor may be selected to have a valuecentered within the range, such as 27 ohms and 43 ohms. In this way,inexpensive low precision components may be used to select amongst arange of high precision outputs. The select value may be used directlyas a variable value to control a device characteristic of the crystaloscillator emulator 120. The variable value may also be determinedindirectly from the select value.

A storage circuit 127 may include variable values that may be selectedas a function of the select value. The storage circuit 127 may be anytype of storage structure including content addressable memory, staticand dynamic memory, and look-up tables.

For the case that the measurement circuit 126 generates output valuesthat have a one-to-one correspondence to the external impedance values,a digital value determiner 128 may then set the output value to a selectvalue that corresponds to a range of external impedance values.

FIG. 7A shows a relationship between groups of impedance values 150 andassociated select values 154. The groups of impedance values 150 mayhave a one-to-one correspondence to groups of digital output values 152which are converted to the select values 154 associated with each of thegroups of impedance values 150. The impedance values ranging from aminimum impedance value to a maximum impedance are separated in intothree or more groups, with each group having a nominal impedance. Thenominal impedance values of each of the groups may be selected to have aspacing between nominal impedance values. Here, the nominal values, 27ohms and 43 ohms, of the groups of impedance values have a spacing of 16ohms. The spacing between the groups of impedance values is preferablybased on geometric progression, however any mathematical relationshipmay be used to establish spacing between the groups such as logarithmic,linear, and exponential. The spacing between impedance groups may bebased on any impedance value of the groups including a nominal value, anaverage value, a mean value, a starting value, and an ending value.Factors that influence selection of the impedance range of the groupsand the spacing may include various tolerances such as the tolerance ofthe external impedance, the tolerance of internal voltage and currentsources, and the tolerance of the measurement circuit. The tolerancesmay for example be caused by process, temperature, and power variations.

FIG. 7B shows a relationship between ranges of impedance values 156 andassociated select values 158. The ranges of impedance values 156 have adirect correspondence to the select values 158. The impedance valuesranging from a minimum impedance value to a maximum impedance areseparated in into three or more groups, with each group having a nominalimpedance. The nominal impedance values of each of the groups may beselected to have a spacing between nominal impedance values. Here, thenominal values, 27 ohms and 43 ohms, of the groups of impedance valueshave a spacing of 16 ohms. This direct correspondence between the rangesof impedance values 156 and associated select values 158 may beimplemented by, for example, a nonlinear analog to digital converter(not shown).

Referring back to FIG. 6, an address generator 130 may determine memorylocations corresponding to the digital output values associated withexternal impedances connected to the select pins. The memory locationsmay be grouped in any manner such as a list for a single select pin, alookup table for two select pins, and a third order table for threeselect pins.

A controller 132 may set a device characteristic of the crystaloscillator emulator 120 as a function of the variable value. Thevariable value may be generated directly by the measurement circuit,determined indirectly from the select value, and determined from thecontents of a memory location corresponding to the external impedancevalues connected to the select pins.

The select pin 124 may also be used for implementing an additionalfunction such as power down (PD), power enable, mode selection, reset,and synchronous operation. In this aspect, the select pin 124 becomes amulti-purpose select pin 124 for configuring the crystal oscillatoremulator 120 as well as implementing the additional function.

In one aspect, a first range of impedance values connected to themulti-purpose select pin 124 may be used to configure the crystaloscillator emulator 120, while operation of the additional function maybe controlled by a voltage or current impressed on the multi-purposeselect pin 124, or impedance values outside the first range of impedancevalues.

FIG. 8 shows an aspect of an oscillator assembly 200 to generate anoutput having a periodic waveform. The oscillator assembly 200 includesa crystal oscillator emulator 202 to drive a phase lock loop (PLL) 204.The crystal oscillator emulator 202 may be similar in function andstructure to the aspects of the crystal oscillator emulators describedabove. The oscillator assembly 200 may include any type of PLL 204 suchas digital PLLs and analog PLLs.

Multi-purpose select pins 206 and 208 may be used for selection of theoperating parameters for the PLL 204 such as the divider factor. Themulti-purpose select pins 206 and 208 may also be used for control andoperation of the crystal oscillator emulator 202 such as outputfrequency selection and reception of a reference clock for calibration.External resistors 210 and 212 may be connected to the multi-purposeselect pins 206 and 208 to select the operating frequency. The ranges ofvalues of the external resistors 210 and 212 correspond to the selectionof different operating frequencies. Each external resistor 210 and 212may be used to select one of 16 predetermined operating frequencies. Incombination, the external resistors 210 and 212 may select from amongst256 operating frequencies. To control multiple functions, each of themulti-purpose select pins 206 and 208 may receive signals withindifferent voltage ranges. For example, one multi-purpose select pin 206may connect to an external resistor 210 across which a voltage in therange of 0 to 2 volts may be developed to determine the resistance, andthe multi-purpose select pin 206 may also receive a reference clocksignal operating in a range of 2 to 3 volts. A decoder 214 may detectsignals on the multi-purpose select pins 206 and 208.

FIG. 9 shows a spread spectrum oscillator 300 for generating an outputsignal having a variable frequency. The spread spectrum oscillator 300includes a crystal oscillator emulator 302 connected to a PLL 304. Afrequency control device connected to the crystal oscillator emulator302 may dynamically control the output frequency of the crystaloscillator emulator 302. The frequency control device may be any deviceor technique including a varactor, controlling the bias current sourceof the semiconductor oscillator, and controlling the control inputvoltage applied to the resonant capacitors of the semiconductoroscillator.

FIG. 10 shows the operation of an aspect of a crystal oscillatoremulator. At block 400, a semiconductor oscillator is provided forgenerating an output signal having a periodic waveform. Continuing toblock 402, the semiconductor oscillator may be calibrated to generate aconstant frequency over a predetermined range of temperature. In oneaspect, the calibration may include varying the temperature of thesemiconductor die over a predetermined temperature range and measuringcalibration information for maintaining a constant output frequency. Thedie temperature may be measured in the vicinity of the semiconductoroscillator. The calibration information may include control input valuesversus die temperatures for maintaining a constant output frequency. Thecalibration information may be stored in non-volatile memory on thesemiconductor die. At block 404, an operating frequency may bedetermined by probing an external component. Continuing to block 406,the semiconductor oscillator generates an output signal having anoperating frequency. At block 408, the temperature of the semiconductordie is determined in the vicinity of the semiconductor oscillator.Continuing to block 410, the semiconductor die may be heated or cooledto control the die temperature to one or more predetermined temperaturelevels. At block 412, the control input may be controlled as a functionof the die temperature to compensate for changes in the operatingfrequency of the output signal caused by temperature changes. The storedcalibration information may be used to control the control input. Thecalibration information may be used directly for die temperatures thatcorrespond to stored temperatures. For other die temperatures, thecontrol input value may be extrapolated from the stored calibrationinformation. Continuing to block 414, the frequency of the output signalmay be dynamically varied as a function of a frequency control signal.

FIG. 11 shows an aspect of a low power oscillator 320 for generating aperiodic signal. The low power oscillator 320 includes a crystaloscillator emulator 322 to calibrate an active silicon oscillator 324.The crystal oscillator emulator 322 is normally in the off state toreduce power consumption. At predetermined intervals, the crystaloscillator emulator 322 is switched to the powered on state to calibratethe active silicon oscillator 324. The active silicon oscillator 324consumes less power than the crystal oscillator emulator 322, sooperating the active silicon oscillator 324 continuously while onlyoperating the crystal oscillator emulator 322 intermittently reduces theoverall power consumption of the low power oscillator 320. Any type ofactive silicon oscillator may be used including ring oscillators and RCoscillators. The crystal oscillator emulator 324 may be configured inaccordance with any of the aspects of the invention as described andshown in this specification.

A summer 326 may determine the frequency error between the activesilicon oscillator output and the crystal oscillator emulator output. Acontroller 328 may generate a control signal, based on the frequencyerror, to control the frequency of the active silicon oscillator 324.The controller 328 may also receive temperature information from thecrystal oscillator emulator 322. The temperature information may includetemperatures such as the temperature of the semiconductor and theambient temperature. The controller 328 may include calibrationinformation for the active silicon oscillator 324 similar to thecalibration information for the crystal oscillator emulator 322. Thefrequency error may be used to set an initial value for the controlsignal and then the temperature information in combination with theactive silicon oscillator calibration information may be used to updatethe control signal while the crystal oscillator emulator 322 is powereddown. In one aspect, the temperature sensing circuit of the crystaloscillator emulator 322 may remain continuously powered so thatcontinuous temperature information may be supplied to the controller328. The control signal 334 may be either digital or analog. If thecontrol signal is digital, a digital-to-analog converter (DAC) 330 mayconvert the control signal to analog.

A regulator 332 may, in response to the control signal 334, control thesupply of power for the active silicon oscillator 324 to adjust theoperating frequency. The supply of voltage and/or current to the activesilicon oscillator 324 may be controlled. For example, the regulator 332may control the voltage level of the supply voltage.

In operation, the active silicon oscillator 324 is normally in the onstate generating a periodic output signal. The crystal oscillatoremulator 322 is normally in the off state. In the off state, either allor a portion of the crystal oscillator emulator 322 may be powered offto conserve power. At a predetermined time, power is applied to thecrystal oscillator emulator 322. The semiconductor oscillator of thecrystal oscillator emulator 322 is then calibrated with the storedcalibration information. The frequency of the output signal of thecrystal oscillator emulator 322 is compared with the frequency of theoutput signal of the active silicon oscillator 324 to determine thefrequency error of the active silicon oscillator 324. The control signal334 changes in response to the frequency error, causing a shift in thesupply voltage from the voltage regulator 332, leading to a change inthe output frequency of the active silicon oscillator 324, reducing thefrequency error.

FIG. 12 shows an aspect of another low power oscillator 350 forgenerating a periodic signal. The low power oscillator 350 includes acrystal oscillator emulator 352 in communication with a charge pumposcillator 354. The crystal oscillator emulator 352 is normally in thepowered down state to reduce power consumption. During the powered downstate, either all or a portion of the crystal oscillator emulator 352may be powered down. At predetermined intervals, the crystal oscillatoremulator 352 may be powered up and used to calibrate the charge pumposcillator 354. The predetermined intervals may be determined as afunction of any circuit parameter such as operating time, temperaturechange of the semiconductor, ambient temperature change, temperature ofthe semiconductor, and supply voltage change.

The charge pump oscillator 354 may include a charge pump 356, loopfilter 358, voltage controlled oscillator (VCO) 360, and phase detector362. The charge pump oscillator 354 is similar in operation toconventional charge pump oscillators, except that the reference input ofthe phase detector 362 receives a reference clock signal from thecrystal oscillator emulator 352.

A multiplexer 364 receives the output signals from the crystaloscillator emulator 352 and the charge pump oscillator 354. One of theoutput signals is selected and passed through the multiplexer 375 to aphase locked loop 366. The phase locked loop 366 generates an outputsignal as a function of the output signals from the crystal oscillatoremulator 352 and the charge pump oscillator 354.

In operation, the charge pump oscillator 354 is normally in the on stategenerating a periodic output signal. The crystal oscillator emulator 352is normally in the off state. In the off state, either all or a portionof the crystal oscillator emulator 352 may be powered off to reducepower consumption. At a predetermined time, power is applied to thecrystal oscillator emulator 352. The semiconductor oscillator of thecrystal oscillator emulator 352 is then calibrated with the storedcalibration information. The output signal of the crystal oscillatoremulator 352 is compared with the output signal of the charge pumposcillator 354 to determine the phase error of the charge pumposcillator 324. The VCO 360 is then controlled to reduce the phase errorso that the output signal of the charge pump oscillator 354 iscalibrated to the output signal of the crystal oscillator emulator 352.One of the output signals may then be selected and applied to the PLL366.

Referring now to FIGS. 13-15, an integrated circuit 500 includes acrystal oscillator emulator 502 that generates a clock signal. One ormore circuits 504 in the integrated circuit 500 receive the clocksignals. The crystal oscillator emulator 502 can be implemented asdescribed above in conjunction with FIGS. 1-12. The circuits 502 caninclude a processor 512 as shown in FIG. 14 or other circuits. Anexternal component 506 can optionally be used to select the clockfrequency of the crystal oscillator emulator 502 as shown in FIGS. 13and 15.

Referring now to FIGS. 16-18, an integrated circuit 518 includes a clockdivider 520 that generates clock signals at other one or more otherclock frequencies for circuits 522-1, 522-2, . . . , and 522-N(collectively circuits 522). The circuits 522 may be interconnected toeach other in any manner. The clock divider 520 divides the clock by aninteger such as X and/or multiplies the clock signal by Y for 1/X, Yand/or Y/X adjustments. The clock divider 520 may also use one or moreadditional ratios and/or divisors for producing different clock signalsfor other circuits 522. The clock divider 520 outputs N−1 clock signalsas shown to N−1 circuits 522 in the integrated circuit 518.

In FIG. 17, one of the circuits includes a processor 530. The processor530 can be connected to the clock divider 520 instead of and/or inaddition to the crystal oscillator emulator 502. Additional circuits532-1, 532-1, and 532-N communicate with the clock divider 520.

In FIG. 18, the crystal oscillator emulator 502 provides clock signalsfor a processor 530, a graphics processor 540, memory 542 and/or one ormore circuits 544 in the integrated circuit 518. A clock divider (notshown) may also be provided. The processor 530, graphics processor 540,memory 542 and/or other circuits 544 may be interconnected in anysuitable manner.

Referring now to FIG. 19, an integrated circuit 600 includes one or morecircuits 602-1, 602-2, . . . , and 602-N (collectively circuits 602) andthe low power oscillator 320, which operates as described above inconjunction with FIG. 11. One of the circuits may include a processor asshown at 610. A clock divider (not shown) may also be provided asdescribed above.

Integrated circuits (IC) are typically encased in a packaging material.The packaging material may include plastic. The IC substrate may includepads that are connected to leads of a lead frame by bondwires. The ICsubstrate, the bondwires and portions of the leads may be encased in theplastic. The properties of the packaging material that is normally usedin packaging the IC may change over time. The changes may cause anoscillation frequency of an on-chip oscillator to drift over time. Thechanges in the packaging may be due to changes in the dielectric loss ofthe packaging material over time. The changes in the packaging may alsobe due to water absorption of the packaging material at differenthumidity levels. As a result, the packaging material may limit theachievable calibrated accuracy.

Referring now to FIG. 20, an integrated circuit 700 is encapsulated in apackaging material 704 according to the prior art. As can beappreciated, characteristics of the packaging material 704 may changeover time and/or as a function of environmental conditions. For example,when the packaging material 704 includes plastic material, thedielectric loss of the plastic material may change over time, which mayhave an adverse impact upon calibration accuracy. As used herein, theterm dielectric loss refers to loss of energy that eventually produces arise in temperature of a dielectric placed in an alternating electricalfield. Heating is due to “molecular friction” of dipoles within thematerial as the dipoles try to reorient themselves with the oscillating(electrical) field of the incident wave. For example, when heating foodin a microwave, the dipoles associated with water in the food vibrateand are heated. Some materials such as certain plastics are not suitablefor use in microwaves since they absorb too much heat. These materialshave high dielectric loss characteristics. Other materials such as othertypes of plastics experience little or no heating. These materials havelower dielectric loss characteristics. Since the circuits describedherein may operate at microwave frequencies, low dielectric lossmaterials are preferred.

Water absorption of the plastic material over time may also adverselyimpact calibration accuracy. Since water has a high dielectric loss,increased water content in the packaging material tends to increase thedielectric loss of the packaging material. In other features, thepackaging material may also be a low stress material. High stressmaterials tend to warp, which may affect circuit characteristics ofadjacent circuits such as by changing channel lengths. As used herein,the term low stress refers to packaging materials that tend to be stableand not change the electrical characteristics of the integrated circuitdue to changes in stress. In some implementations, the packagingmaterial has a dielectric loss factor (DLF) that is less than or equalto Teflon at the relevant frequency of operation, such as greater than 1GHz.

Referring now to FIG. 21, an integrated circuit 710 with an on-chipsemiconductor oscillator 711 with temperature compensation is shownencapsulated in a packaging material 714 having a low dielectric lossaccording to the present invention. The packaging material 714 may be aplastic packaging material having low dielectric loss. As used herein,the term “low dielectric loss” refers to materials having a dielectricloss that is less than or equal to Teflon at a relevant operatingfrequency of the IC. The operating frequency of the IC may be above 1GHz and/or 2.4 GHz. The packaging material 714 may also compriseTeflon®, Teflon® PolyChloroTriFluoroEthylene (PCTFE), Teflon® Teflon®fluorinated ethylene propylene copolymer (FEP), perfluoroalkoxy) (PFA),Tefzel® and Teflon® copolymer of ethylene and tetrafluoroethylene(ETFE), low dielectric loss plastic, high quality glass, air and/orother materials. Any other packaging materials having dielectric lossthat is less than or equal to Teflon are contemplated. The packagingmaterial also may have relatively low water absorption.

Referring now to FIG. 22, an exemplary implementation of the integratedcircuit package of FIG. 21 is shown in further detail. An integratedcircuit package 718 includes an integrated circuit 724 that includespads 728. Leads 732 of a lead frame 733 are connected by bondwires 734to the pads 728 of the integrated circuit. As can be appreciated, theintegrated circuit includes an on-chip semiconductor oscillator withtemperature compensation as described above. Portions of the leads 732,the bond wires 734 and the integrated circuit 724 are encapsulated in apackaging material 736. The packaging material 736 may be a plasticpackaging material having low dielectric loss. As can be appreciated,other types of packaging such as ball grid array (BGA), flip chip and/orany other suitable packaging technique may be employed in thisembodiment and/or others that precede or follow.

Referring now to FIG. 23, an alternate integrated circuit package 738includes an on-chip, temperature-compensated semiconductor oscillator741 according to the present invention. In this embodiment, thesemiconductor oscillator 741 comprises an integrated circuit inductor742. A glass layer 744 is bonded to the integrated circuit substrate 740using a very thin epoxy layer 750. The epoxy layer 750 may have a lowdielectric loss. The glass layer 744, the epoxy layer 750 and theintegrated circuit substrate 740 are encapsulated in a packagingmaterial 760. In this case, the dielectric loss of the packagingmaterial is less critical due to the distance between the inductor 742and the packaging material 760. Therefore, changes in the dielectricloss and/or other characteristics of the packaging material 760 are lesscritical as a function of time. However, the packaging material can below dielectric loss material. While the glass layer is shown over theentire integrated circuit, the glass layer may be limited to a smallerregion immediately adjacent to the semiconductor oscillator.

Referring now to FIGS. 24 and 25, an alternate integrated circuitpackage including an on-chip semiconductor oscillator according to thepresent invention is shown. This embodiment is similar to that shown anddescribed above in conjunction with FIG. 23. However, the glass layer744 defines a cavity 746. The cavity 746 is adjacent to, aligned withand extends over the inductor 742. An air cavity 752 is formed betweenthe inductor 742 and the glass layer 744. A thin epoxy layer 750 isformed between the glass layer 744 and the integrated circuit substrate740 in areas other than the cavity 746. The glass layer 744 may beetched to define the cavity and dipped in epoxy. Adjacently, the glasslayer may include multiple layers of glass and at least one layer has acavity formed therein.

Referring now to FIG. 26, a capacitor of an on-chip semiconductoroscillator may be adjusted based upon temperature compensation aspreviously described above. As can be appreciated, however, there areother ways of adjusting the oscillating frequency independent fromadjusting the capacitor and/or inductor of the semiconductor oscillator.

Referring now to FIG. 27, an integrated circuit 830 includes afractional phase locked loop 831 with a temperature compensation input.The fractional phase locked loop 831 includes a phase frequency detector836 that receives an output of the integrated circuit oscillator 832,which operates as described above. The phase frequency detector 836generates a differential signal based on a difference between areference frequency and a VCO frequency. The differential signal isoutput to a charge pump 840. An output of the charge pump 840 is inputto an optional loop filter 844. An output of the loop filter 844 isinput to a voltage controlled oscillator (VCO), which generates a VCOoutput having a frequency that is related to a voltage input thereto. Anoutput of the VCO 846 is fed back to a scaling circuit 850. The scalingcircuit 850 selectively divides the VCO frequency by N or N+1. While Nand N+1 divisors are employed, the divisors may have other values.

An output of the scaling circuit 850 is fed back to the phase frequencydetector 836. A temperature sensor 850 measures a temperature of theintegrated circuit 830 in the region near the IC oscillator 832. Thetemperature sensor 850 outputs a temperature signal that is used toaddress calibration information 858 that is stored in memory 856. Theselected calibration information is used to adjust the scaling circuit850. The selected calibration information adjusts a ratio of thedivisors N and N+1 that are used by the scaling circuit 844.

Referring now to FIG. 28, a Delta-Sigma fractional phase locked loop 858is shown for an integrated circuit 860 that includes a temperaturecompensation input. The selected calibration information is used toadjust an output of a Sigma Delta modulator 870. The selectedcalibration information may adjust a modulation between the divisors Nand N+1 that are used by the scaling circuit 844.

Referring now to FIG. 29, a flow chart 900 illustrates steps formeasuring sampling calibration points using a linear curve fittingalgorithm to generate the calibration data. Control begins with step902. In step 904, control measures sample calibration points at aplurality of temperatures. In step 906, linear curve fitting algorithmsare used to generate curves for other temperature points between thesample points. In step 908, control ends.

Referring now to FIG. 30, a flow chart 920 illustrating steps formeasuring sampling calibration points and using higher order curvefitting algorithms to generate the calibration data. The steps shown inFIG. 29 may be implemented using a computer that includes a processorand memory. Control begins with step 902. In step 924, control measuressample calibration points at a plurality of temperatures. In step 926,higher order curve fitting algorithms are used to generate curves forother temperature points between the sample points. In step 928, controlends.

Referring now to FIGS. 31A-31G, various exemplary implementations of thepresent invention are shown. Referring now to FIG. 31A, the presentinvention can be implemented in a hard disk drive 1000. The presentinvention may implement any integrated circuit such as either or bothsignal processing and/or control circuits, which are generallyidentified in FIG. 31A at 1002. In some implementations, the signalprocessing and/or control circuit 1002 and/or other circuits (not shown)in the HDD 1000 may process data, perform coding and/or encryption,perform calculations, and/or format data that is output to and/orreceived from a magnetic storage medium 1006.

The HDD 1000 may communicate with a host device (not shown) such as acomputer, mobile computing devices such as personal digital assistants,cellular phones, media or MP3 players and the like, and/or other devicesvia one or more wired or wireless communication links 1008. The HDD 1000may be connected to memory 1009 such as random access memory (RAM), lowlatency nonvolatile memory such as flash memory, read only memory (ROM)and/or other suitable electronic data storage.

Referring now to FIG. 31B, the present invention can be implemented in adigital versatile disc (DVD) drive 1010. The present invention mayimplement any integrated circuit such as either or both signalprocessing and/or control circuits, which are generally identified inFIG. 31B at 1012, and/or mass data storage of the DVD drive 1010. Thesignal processing and/or control circuit 1012 and/or other circuits (notshown) in the DVD 1010 may process data, perform coding and/orencryption, perform calculations, and/or format data that is read fromand/or data written to an optical storage medium 1016. In someimplementations, the signal processing and/or control circuit 1012and/or other circuits (not shown) in the DVD 1010 can also perform otherfunctions such as encoding and/or decoding and/or any other signalprocessing functions associated with a DVD drive.

The DVD drive 1010 may communicate with an output device (not shown)such as a computer, television or other device via one or more wired orwireless communication links 1017. The DVD 1010 may communicate withmass data storage 1018 that stores data in a nonvolatile manner. Themass data storage 1018 may include a hard disk drive (HDD). The HDD mayhave the configuration shown in FIG. 31A. The HDD may be a mini HDD thatincludes one or more platters having a diameter that is smaller thanapproximately 1.8″. The DVD 1010 may be connected to memory 1019 such asRAM, ROM, low latency nonvolatile memory such as flash memory and/orother suitable electronic data storage.

Referring now to FIG. 31C, the present invention can be implemented in ahigh definition television (HDTV) 1020. The present invention mayimplement any integrated circuit such as either or both signalprocessing and/or control circuits, which are generally identified inFIG. 31E at 1022, a WLAN interface and/or mass data storage of the HDTV1020. The HDTV 1020 receives HDTV input signals in either a wired orwireless format and generates HDTV output signals for a display 1026. Insome implementations, signal processing circuit and/or control circuit1022 and/or other circuits (not shown) of the HDTV 1020 may processdata, perform coding and/or encryption, perform calculations, formatdata and/or perform any other type of HDTV processing that may berequired.

The HDTV 1020 may communicate with mass data storage 1027 that storesdata in a nonvolatile manner such as optical and/or magnetic storagedevices. At least one HDD may have the configuration shown in FIG. 31Aand/or at least one DVD may have the configuration shown in FIG. 31B.The HDD may be a mini HDD that includes one or more platters having adiameter that is smaller than approximately 1.8″. The HDTV 1020 may beconnected to memory 1028 such as RAM, ROM, low latency nonvolatilememory such as flash memory and/or other suitable electronic datastorage. The HDTV 1020 also may support connections with a WLAN via aWLAN network interface 1029.

Referring now to FIG. 31D, the present invention implements anyintegrated circuit in a control system of a vehicle 1030, a WLANinterface and/or mass data storage of the vehicle control system. Insome implementations, the present invention implement a powertraincontrol system 1032 that receives inputs from one or more sensors suchas temperature sensors, pressure sensors, rotational sensors, airflowsensors and/or any other suitable sensors and/or that generates one ormore output control signals such as engine operating parameters,transmission operating parameters, and/or other control signals.

The present invention may also be implemented in other control systems1040 of the vehicle 1030. The control system 1040 may likewise receivesignals from input sensors 1042 and/or output control signals to one ormore output devices 1044. In some implementations, the control system1040 may be part of an anti-lock braking system (ABS), a navigationsystem, a telematics system, a vehicle telematics system, a lanedeparture system, an adaptive cruise control system, a vehicleentertainment system such as a stereo, DVD, compact disc and the like.Still other implementations are contemplated.

The powertrain control system 1032 may communicate with mass datastorage 1046 that stores data in a nonvolatile manner. The mass datastorage 1046 may include optical and/or magnetic storage devices forexample hard disk drives HDD and/or DVDs. At least one HDD may have theconfiguration shown in FIG. 31A and/or at least one DVD may have theconfiguration shown in FIG. 31B. The HDD may be a mini HDD that includesone or more platters having a diameter that is smaller thanapproximately 1.8″. The powertrain control system 1032 may be connectedto memory 1047 such as RAM, ROM, low latency nonvolatile memory such asflash memory and/or other suitable electronic data storage. Thepowertrain control system 1032 also may support connections with a WLANvia a WLAN network interface 1048. The control system 1040 may alsoinclude mass data storage, memory and/or a WLAN interface (all notshown).

Referring now to FIG. 31E, the present invention can be implemented in acellular phone 1050 that may include a cellular antenna 1051. Thepresent invention may implement any integrated circuit such as either orboth signal processing and/or control circuits, which are generallyidentified in FIG. 31E at 1052, a WLAN interface and/or mass datastorage of the cellular phone 1050. In some implementations, thecellular phone 1050 includes a microphone 1056, an audio output 1058such as a speaker and/or audio output jack, a display 1060 and/or aninput device 1062 such as a keypad, pointing device, voice actuationand/or other input device. The signal processing and/or control circuits1052 and/or other circuits (not shown) in the cellular phone 1050 mayprocess data, perform coding and/or encryption, perform calculations,format data and/or perform other cellular phone functions.

The cellular phone 1050 may communicate with mass data storage 1064 thatstores data in a nonvolatile manner such as optical and/or magneticstorage devices for example hard disk drives HDD and/or DVDs. At leastone HDD may have the configuration shown in FIG. 31A and/or at least oneDVD may have the configuration shown in FIG. 31B. The HDD may be a miniHDD that includes one or more platters having a diameter that is smallerthan approximately 1.8″. The cellular phone 1050 may be connected tomemory 1066 such as RAM, ROM, low latency nonvolatile memory such asflash memory and/or other suitable electronic data storage. The cellularphone 1050 also may support connections with a WLAN via a WLAN networkinterface 1068.

Referring now to FIG. 31F, the present invention can be implemented in aset top box 1080. The present invention may implement any integratedcircuit such as either or both signal processing and/or controlcircuits, which are generally identified in FIG. 31F at 1084, a WLANinterface and/or mass data storage of the set top box 1080. The set topbox 1080 receives signals from a source such as a broadband source andoutputs standard and/or high definition audio/video signals suitable fora display 1088 such as a television and/or monitor and/or other videoand/or audio output devices. The signal processing and/or controlcircuits 1084 and/or other circuits (not shown) of the set top box 1080may process data, perform coding and/or encryption, performcalculations, format data and/or perform any other set top box function.

The set top box 1080 may communicate with mass data storage 1090 thatstores data in a nonvolatile manner. The mass data storage 1090 mayinclude optical and/or magnetic storage devices for example hard diskdrives HDD and/or DVDs. At least one HDD may have the configurationshown in FIG. 31A and/or at least one DVD may have the configurationshown in FIG. 31B. The HDD may be a mini HDD that includes one or moreplatters having a diameter that is smaller than approximately 1.8″. Theset top box 1080 may be connected to memory 1094 such as RAM, ROM, lowlatency nonvolatile memory such as flash memory and/or other suitableelectronic data storage. The set top box 1080 also may supportconnections with a WLAN via a WLAN network interface 1096.

Referring now to FIG. 31G, the present invention can be implemented in amedia player 1100. The present invention may implement any integratedcircuit such as either or both signal processing and/or controlcircuits, which are generally identified in FIG. 31G at 1104, a WLANinterface and/or mass data storage of the media player 1100. In someimplementations, the media player 1100 includes a display 1107 and/or auser input 1108 such as a keypad, touchpad and the like. In someimplementations, the media player 1100 may employ a graphical userinterface (GUI) that typically employs menus, drop down menus, iconsand/or a point-and-click interface via the display 1107 and/or userinput 1108. The media player 1100 further includes an audio output 1109such as a speaker and/or audio output jack. The signal processing and/orcontrol circuits 1104 and/or other circuits (not shown) of the mediaplayer 1100 may process data, perform coding and/or encryption, performcalculations, format data and/or perform any other media playerfunction.

The media player 1100 may communicate with mass data storage 1110 thatstores data such as compressed audio and/or video content in anonvolatile manner. In some implementations, the compressed audio filesinclude files that are compliant with MP3 format or other suitablecompressed audio and/or video formats. The mass data storage may includeoptical and/or magnetic storage devices for example hard disk drives HDDand/or DVDs. At least one HDD may have the configuration shown in FIG.31A and/or at least one DVD may have the configuration shown in FIG.31B. The HDD may be a mini HDD that includes one or more platters havinga diameter that is smaller than approximately 1.8″. The media player1100 may be connected to memory 1114 such as RAM, ROM, low latencynonvolatile memory such as flash memory and/or other suitable electronicdata storage. The media player 1100 also may support connections with aWLAN via a WLAN network interface 1116. Still other implementations inaddition to those described above are contemplated.

Referring now to FIGS. 32A-32D, an integrated circuit package is shownthat incorporates an annealed glass paste or epoxy as a layer and/or“islands” adjacent to one or more selected features of a silicon wafer.One or more “islands” of the annealed glass paste or epoxy layer can bemade on portions of one or both sides of the silicon wafer. In FIG. 32A,an alternate integrated circuit package 1200 includes a silicon wafer1204. An annealed glass paste layer or portions 1206 is/are formed onthe silicon wafer 1204. A molding material 1208 may be used toencapsulate all or part of the silicon wafer 1204. The annealed glasspaste layer 1206 also reduces the change in stress over time. Theannealed glass paste layer 1206 tends to isolate all or part of thesilicon wafer 1204 from variations in the dielectric properties such asdielectric loss of the molding material 1208.

The silicon wafer 1204 may include a semiconductor oscillator asdescribed above. The annealed glass paste layer 1206 may include a glasspaste having a relatively low annealing temperature. The low annealingtemperature may be lower than a temperature that would damage thesilicon wafer 1204. The glass paste layer 1206 may include glass fritpaste. The glass paste layer may be applied in any suitable manner. Theglass paste layer may be applied using a screen printing approach, adipping approach, a masking approach, and/or using any other suitableapproach.

In FIG. 32B, an alternate integrated circuit package 1210 includes aconductive material layer or coating 1212 that is applied to the glasspaste or epoxy layer 1204. The conductive material layer 1212 mayinclude a layer of conductive epoxy. The conductive material layer 1212may be applied as a liquid and cured. The conductive material layer 1212may include conductive epoxy paint. The conductive material layer 1212may be applied in any suitable fashion including dipping the siliconwafer 1204 into a container such as a dish that contains the conductivematerial. The conductive material layer 1212 tends to reduceelectromagnetic interference from external devices.

In FIG. 32C, an integrated circuit package 1220 includes the annealedglass paste layer 1206, which is applied to selected portions of thesilicon wafer 1204. In FIG. 32D, an integrated circuit package 1230includes the annealed glass paste or epoxy portions 1206 and theconductive material 1212. The conductive material 1212 may cover theannealed glass paste layer 1206 while touching or not touching thesilicon wafer 1204.

Referring now to FIGS. 33A-33D, alternate integrated circuit packagesare show. In FIG. 33A, an alternate integrated circuit package 1240includes the annealed glass paste layer 1206 and the conductive materiallayer 1212, which are located adjacent to circuit components 1242 of thesilicon wafer 1204. In FIG. 33B, an alternate integrated circuit package1250 includes the annealed glass paste layer 1206 and conductivematerial layer 1212, which are located adjacent to an oscillator 1252 ofthe silicon wafer 1204.

In FIG. 33C, an alternate integrated circuit package 1260 includes theannealed glass paste layer 1206 and conductive material layer 1212,which are located adjacent to an inductor 1262 of the silicon wafer1204. The inductor 1262 may be an on-chip inductor such as a spiralinductor. In FIG. 33D, an alternate integrated circuit package 1270includes the annealed glass paste layer 1206 and conductive materiallayer 1212, which are located adjacent to oscillator circuit 1272 withan inductor 1274.

The annealed glass paste layer also tends to reduce the change in stressover time that can occur. The annealed glass paste layer isolates all orpart of the silicon wafer from variations in the dielectric propertiessuch as dielectric loss of the molding material. This can beparticularly advantageous when attempting to calibrate using temperatureas described above.

Referring now to FIGS. 34A-34D, alternate integrated circuit packagesare shown that include annealed glass paste and/or epoxy portions and aglass or silicon layer that create an air gap above portions of asilicon wafer. In FIGS. 34A-34B, integrated circuit packages 1300 and1330 include a silicon wafer 1304. Annealed glass paste portions 1306are formed on the silicon wafer 1304 in a spaced apart relationship. TheAGP portions 1306 may be formed as described above. A molding material1308 may be used. Post-processing of the AGP portions 1306 may beperformed such as polishing or other steps to provide a planar outersurface.

A glass or silicon layer 1310 is supported above the silicon wafer 1304by the AGP portions 1306. Epoxy or other adhesive binding material maybe used to attach the glass or silicon layer 1310 to the AGP portions1306. AGP portions 1306 and the glass or silicon layer 1310 form an airgap 1324 above an oscillator 1320 in FIG. 34A and/or any other circuit1322 in FIG. 34B. The air gap 1324 provides the material (air) havingthe lowest possible dielectric loss. In contrast, when crystaloscillators are used, the air is needed to allow the crystal toresonate—in other words, the air is used to allow mechanicaloscillation.

In FIGS. 34C-34D, integrated circuit packages 1340 and 1360 include asilicon wafer 1304. Epoxy portions 1342 are formed on the silicon wafer1304 in a spaced apart relationship. The epoxy portions 1342 may beformed as described above. Post-processing of the epoxy portions 1306may be performed such as polishing or other steps to provide a planarouter surface. A glass or silicon layer 1310 is supported above thesilicon wafer 1304 by the epoxy portions 1342. Epoxy or other adhesivebinding material may be used to attach the glass or silicon layer 1310to the epoxy portions 1342. The portions 1306 and the layer 1310 form anair gap 1324 above an oscillator 1320 in FIG. 34C and/or any othercircuit 1322 in FIG. 34D.

Referring now to FIGS. 35A-35B, alternate integrated circuit packagesare shown that include a glass or silicon portion that creates an airgap. In FIG. 35A, an integrated circuit package the 1380 includes a“C”-shaped glass or silicon portion 1382 that defines an air gap 1384.The “C”-shaped glass or silicon portion 1382 may include multiplesections that are joined together. The air gap 1384 is located above anoscillator 1320. In FIG. 35B, an integrated circuit package 1390includes a “C”-shaped glass or silicon layer 1382 that defines an airgap 1384. The air gap 1384 is located above a circuit 1322.

Referring now to FIGS. 36A-36C, methods for making integrated circuitpackages described above are shown. An integrated circuit structure 1400includes a silicon wafer 1404, a plurality of spaced AGP and/or epoxyportions 1410A and 1410B (collectively portions 1410), and a glass orsilicon layer 1408. The integrated circuit structure 1400 is cut intosections along dotted cutlines 1414 to create multiple integratedcircuits, which can be packaged in a molding material (not shown) asdescribed above.

In FIG. 36B, the silicon wafer 1404 may include one or more bond pads1420. Cutting of the layer 1408 at 1414-1 and 1414-2 may be offset fromthe cutting of the silicon wafer at 1414-3 to provide clearance forattaching bondwires (not shown) to the bond pads 1420. In FIG. 36C, oneof the integrated circuits 1450 is shown after being separated from theintegrated circuit structure 1400.

Referring now to FIGS. 37A-37B, an integrated circuit package 1450includes a silicon wafer with spaced annealed glass paste and/or epoxyportions 1410 that have been coated with a layer of conductive material1456′ are shown. In FIG. 37A, the portions 1410 are dipped into acontainer 1454 that contains the conductive material 1456. The siliconwafer 1408 may be diced along one or more cutlines 1462 and may includebond pads 1460 as shown.

Referring now to FIG. 38, steps of a method 1500 for fabricating theintegrated circuit packaging of FIGS. 32A-33D are shown. Control beginsin step 1502. In step 1504, a glass paste layer 1206 is applied to oneor more surfaces of the silicon wafer 1204 and/or select areas of thesilicon wafer 1204. In step 1506, the glass paste layer 1204 is annealedby placing the silicon wafer 1204 and the glass paste layer 1204 in anoven. The temperature of the oven may be set to a temperature that issufficient to cure the glass paste layer 1204. For example, atemperature of around 400° C. for a predetermined period is sufficientto anneal the glass frit paste while not damaging the silicon wafer1204. In step 1508, the conductive material layer 1212 is applied to theannealed glass paste layer 1204. In step 1510, all or part of thesilicon wafer 1204 is encased in a molding material 1208 such asplastic, other materials described herein, and/or other suitable moldingmaterials. In step 1520, control ends.

In each of the foregoing embodiments, the silicon wafer may be replacedby other wafers or other substrates and the annealed glass paste can bereplaced by epoxy.

A number of embodiments of the invention have been described.Nevertheless, it will be understood that various modifications may bemade without departing from the spirit and scope of the invention.Accordingly, other embodiments are within the scope of the followingclaims.

1. An integrated circuit (IC) package, comprising: an IC wafer; and afirst portion that is arranged adjacent to said IC wafer; a secondportion that is arranged adjacent to said IC wafer and that is spacedfrom said first portion, wherein said first and second portions compriseat least one of annealed glass paste (AGP) and epoxy; and a layer thatis arranged adjacent to said first and second portions and that createsan air gap between said layer, said first and second portions and saidIC wafer.
 2. The IC package of claim 1 wherein said IC wafer comprises asilicon wafer.
 3. The IC package of claim 1 further comprising a moldingmaterial that encapsulates at least part of said IC wafer, said layerand said first and second portions.
 4. The IC package of claim 1 whereinsaid layer comprises at least one of glass and silicon.
 5. The ICpackage of claim 1 further comprising a conductive material that isarranged adjacent to said first and second portions.
 6. The IC packageof claim 2 wherein said silicon wafer comprises a circuit component,wherein said air gap is arranged between said circuit component, saidlayer and said first and second portions.
 7. The IC package of claim 6wherein said circuit component comprises at least one of an oscillatorand an inductor.
 8. The IC package of claim 7 wherein said inductorcomprises a spiral inductor.
 9. The IC package of claim 1 wherein saidfirst and second portions comprises glass frit.
 10. The IC package ofclaim 1 wherein said first and second portions are applied to saidsilicon wafer using one of a screen printing, dipping and masking. 11.The IC package of claim 5 wherein said conductive material comprises oneof a conductive epoxy and a conductive epoxy paint.
 12. The IC packageof claim 5 wherein said conductive material is applied to said first andsecond portions by dipping said at least part of said IC package in acontainer containing said conductive material.
 13. The IC package ofclaim 1 wherein said layer has a first width that is less than a secondwidth of said silicon wafer.
 14. The IC package of claim 1 wherein saidIC wafer comprises bond pads.
 15. The IC package of claim 1 wherein saidlayer has a first width that is less than a second width of said siliconwafer and further comprising bond pads that are located in an outerregion of said silicon wafer.
 16. A method of providing an integratedcircuit (IC) package, comprising: providing an IC wafer; and arranging afirst portion adjacent to said IC wafer; arranging a second portionadjacent to said IC wafer and spaced from said first portion, whereinsaid first and second portions comprise at least one of annealed glasspaste (AGP) and epoxy; and arranging a layer adjacent to said first andsecond portions, wherein said layer creates an air gap between saidlayer, said first and second portions and said IC wafer.
 17. The methodof claim 16 wherein said IC wafer comprises a silicon wafer.
 18. Themethod of claim 16 further comprising encapsulating at least part ofsaid IC wafer, said layer and said first and second portions.
 19. Themethod of claim 16 wherein said layer comprises at least one of glassand silicon.
 20. The method of claim 16 further comprising arranging aconductive material adjacent to said first and second portions.
 21. Themethod of claim 16 further comprising arranging said air gap betweensaid circuit component, said layer and said first and second portions.22. The method of claim 21 wherein said circuit component comprises atleast one of an oscillator and an inductor.
 23. The method of claim 22wherein said inductor comprises a spiral inductor.
 24. The method ofclaim 16 wherein said first and second portions comprise glass frit. 25.The method of claim 16 further comprising applying said first and secondportions to said silicon wafer using one of a screen printing, dippingand masking.
 26. The method of claim 20 wherein said conductive materialcomprises one of a conductive epoxy and a conductive epoxy paint. 27.The method of claim 16 wherein said layer has a first width that is lessthan a second width of said silicon wafer.
 28. The method of claim 16further comprising providing bond pads on said IC wafer in an outerregion of said silicon wafer.